Patent Number: 7,089,351

Title: Semiconductor memory device for preventing a late write from disturbing a refresh operation

Abstract: A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

Inventors: Takahashi; Hiroyuki (Kanagawa, JP), Nakagawa; Atsushi (Kanagawa, JP), Inaba; Hideo (Kanagawa, JP)

Assignee: NEC Electronics Corporation

International Classification: G06F 12/16 (20060101)

Expiration Date: 8/08/02018