Patent Number: 7,089,366

Title: Cache flushing

Abstract: Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

Inventors: Horrigan; John W. (Mountain View, CA), Thangavelu; Namasivayam (San Jose, CA), Vargese; George (Folsom, CA), Holscher; Brian (Hillsboro, OR)

Assignee: Intel Corporation

International Classification: G06F 12/12 (20060101); G06F 15/78 (20060101)

Expiration Date: 8/08/02018