Patent Number: 7,089,373

Title: Shadow register to enhance lock acquisition

Abstract: A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

Inventors: Day; Michael Norman (Round Rock, TX), Kim; Roy Moonseuk (Austin, TX), Nutter; Mark Richard (Austin, TX), Okawa; Yasukichi (Austin, TX), Truong; Thuong Quang (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 8/08/02018