Patent Number: 7,089,409

Title: Interface to a memory system for a processor having a replay system

Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

Inventors: Merchant; Amit A. (Portland, OR), Boggs; Darrell D. (Aloha, OR), Sager; David J. (Portland, OR)

Assignee: Intel Corporation

International Classification: G06F 9/48 (20060101)

Expiration Date: 8/08/02018