Patent Number: 7,089,430

Title: Managing multiple processor performance states

Abstract: In one embodiment of the invention, a performance information associated with a processor is read. A processor performance table that corresponds to the performance information is located. The performance table includes a plurality of performance parameters to control performance of the processor. A performance state (PS) structure is updated using one of the processor performance table and a default table.

Inventors: Cooper; Barnes (Beaverton, OR)

Assignee: Intel Corporation

International Classification: G06F 1/26 (20060101); G06F 1/32 (20060101)

Expiration Date: 8/08/02018