Patent Number: 7,089,442

Title: Fault-tolerant clock generator

Abstract: A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.

Inventors: Chang; Kun-Yung K. (Los Altos, CA), Horowitz; Mark A. (Menlo Park, CA)

Assignee: Rambus Inc.

International Classification: G06F 1/04 (20060101)

Expiration Date: 8/08/02018