Patent Number: 7,089,462

Title: Early clock fault detection method and circuit for detecting clock faults in a multiprocessing system

Abstract: An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.

Inventors: Floyd; Michael Stephen (Austin, TX), Reick; Kevin Franklin (Round Rock, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 11/00 (20060101); G06F 11/30 (20060101)

Expiration Date: 8/08/02018