Patent Number: 7,089,463

Title: Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test

Abstract: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Inventors: Baeg; Sang Hyeon (Cupertino, CA), Chung; Sung Soo (San Jose, CA)

Assignee: Cisco Technology Inc.

International Classification: G01R 31/28 (20060101)

Expiration Date: 8/08/02018