Patent Number: 7,101,755

Title: Gate conductor isolation and method for manufacturing same

Abstract: A method for processing a semiconductor device includes providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate. The method includes stripping the pad nitride, depositing an array top oxide layer over the pad oxide formed on the semiconductor substrate in the array area and the support area, and planarizing the array top oxide to a top of the shallow trench isolation oxide in the support area and to a deep trench poly stud of the deep trench transistor in the array area. The method further includes forming a wordline stack comprising a nitride layer, a gate conductor and an insulator, and etching the array top oxide, forming a passing wordline bridge through the array area supported on the shallow trench isolation oxide.

Inventors: Beintner; Jochen (Wappingers Falls, NY)

Assignee: Infineon Technologies AG

International Classification: H01L 21/8242 (20060101)

Expiration Date: 9/05/02018