Patent Number: 7,101,758

Title: Poly-etching method for split gate flash memory cell

Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.

Inventors: Lee; Hsiang-Fan (Hsin-Chu, TW), Wang; Shih-Wei (Hsin-Chu, TW), Lin; Yi-Jiun (Taipei, TW), Chu; Kuo-Wei (Hsin-Chu, TW), Kuo; Ching-Sen (Taipei, TW), Ho; Chia-Tong (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

International Classification: H01L 21/8247 (20060101)

Expiration Date: 9/05/02018