Patent Number: 7,101,778

Title: Transmission lines for CMOS integrated circuits

Abstract: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

Inventors: Forbes; Leonard (Corvallis, OR), Cloud; Eugene H. (Boise, ID), Ahn; Kie Y. (Chappaqua, NY)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/44 (20060101)

Expiration Date: 9/05/02018