Patent Number: 7,101,807

Title: Method of fabricating semiconductor device

Abstract: In the step of forming a gate electrode in the region having the line width in which the miniaturization has been progressed, the present invention provides a method of fabricating a thin film transistor (TFT) whose patterning margin can be enlarged without requiring carrying out the photolithography multiple times. According to a fabricating method of the present invention, the mask pattern of the first layer and the mask pattern of the second layer can be formed in a self-aligned process and as a mask pattern which is analog and whose size are different from each other by performing the photolithography once. The hut shape gate can be formed in a self-aligned process by setting the line width located on the active layer so as to be Li in the mask pattern of the first layer, and so as to be L' in the mask pattern of the second layer, and by in turn carrying out the anisotropic etching using the mask pattern of the second layer and the anisotropic etching using the mask pattern of the first layer. Therefore, the problem of a fabricating method being complex along with the miniaturization of a TFT can be solved by reducing the number of reticles using in the fabricating steps.

Inventors: Ishikawa; Akira (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

International Classification: H01L 21/302 (20060101); H01L 21/461 (20060101)

Expiration Date: 9/05/02018