Patent Number: 7,102,153

Title: Strained silicon forming method with reduction of threading dislocation density

Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed Si.sub.xGe.sub.1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.

Inventors: Chen; Pang-Shiu (Hsinchu, TW), Lee; Sheng-Wei (Taipei, TW), Chen; Lih-Juann (Hsinchu, TW), Liu; Chee-Wee (Taipei, TW)

Assignee: Industrial Technology Research Institute

International Classification: H01L 29/06 (20060101)

Expiration Date: 9/05/02018