Patent Number: 7,102,194

Title: High voltage and low on-resistance LDMOS transistor having radiation structure and isolation effect

Abstract: A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.

Inventors: Huang; Chih-Feng (Jhubei, TW), Yang; Ta-yung (Milpitas, CA), Lin; Jenn-yu G. (Taipei, TW), Chien; Tuo-Hsin (Tucheng, TW)

Assignee: System General Corp.

International Classification: H01L 29/94 (20060101)

Expiration Date: 9/05/02018