Patent Number: 7,102,241

Title: Leadless semiconductor package

Abstract: A leadless semiconductor package disposed on a substrate includes a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

Inventors: Tao; Su (Kaohsiung, TW)

Assignee: Advanced Semiconductor Engineering, Inc.

International Classification: H01L 23/29 (20060101); H01L 23/48 (20060101)

Expiration Date: 9/05/02018