Patent Number: 7,102,402

Title: Circuit to manage and lower clock inaccuracies of integrated circuits

Abstract: A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

Inventors: Kurd; Nasser A. (Portland, OR), Barkatullah; Javed S. (Portland, OR), Dike; Charles (Hillsboro, OR)

Assignee: Intel Corporation

International Classification: H03L 7/06 (20060101)

Expiration Date: 9/05/02018