Patent Number: 7,102,407

Title: Programmable clock delay circuit

Abstract: A delay circuit. The delay circuit includes a first circuit, a falling edge delay circuit and a rising edge delay circuit. The first circuit includes a circuit input for receiving a reference signal and a circuit output for outputting a delayed signal. The falling edge delay circuit is coupled to the first circuit to control delay of a falling edge of the reference signal. The rising edge delay circuit is coupled to the first circuit to control delay of a rising edge of the reference signal.

Inventors: Slawecki; Darren (Santa Clara, CA)

Assignee: Intel Corporation

International Classification: H03H 11/26 (20060101)

Expiration Date: 9/05/02018