Patent Number: 7,102,408

Title: Information processing apparatus with adjustable system clock

Abstract: An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.

Inventors: Yamaguchi; Kazue (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G06F 1/04 (20060101)

Expiration Date: 9/05/02018