Patent Number: 7,102,544

Title: Method and system for improving memory interface data integrity in PLDs

Abstract: An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.

Inventors: Liu; Hui (San Jose, CA)

Assignee: Altera Corporation

International Classification: H03M 7/34 (20060101)

Expiration Date: 9/05/02018