Patent Number: 7,102,911

Title: Method for improving the read signal in a memory having passive memory elements

Abstract: A method for improving read signals in a memory including passive memory elements provided at crossover locations of word and bit lines, and in which stored digital information is represented by a respective resistance of the memory elements includes: determining logic levels of information bits to be written to the memory elements associated with a respective bit line; inverting the logic levels of the information bits if more than half of information bits to be written to the memory elements associated with the respective bit line have a logic level corresponding to a low-value resistance of the memory elements; writing the information bits to the memory elements; and generating an additional check bit, a logic level of which represents an inverted or non-inverted state of the information bits.

Inventors: Hoffmann; Kurt (Taufkirchen, DE)

Assignee: Infineon Technologies AG

International Classification: G11C 11/00 (20060101)

Expiration Date: 9/05/02018