Patent Number: 7,102,940

Title: Circuit arrangement for latency regulation

Abstract: One embodiment of the invention relates to a circuit arrangement for regulating a latency that is defined as a whole number n of periods T of a reference clock of frequency f.sub.c and is intended to elapse, as of a data transmission command, before the data which are to be transmitted from a data source appear at the end of the data path that is to be passed through and contains a chain of transmission elements having fixed delay times. The frequency f.sub.c may be set in a range from 1/T.sub.max to 1/T.sub.min, where T.sub.min is at least equal to .tau..sub.f/n and .tau..sub.f is equal to the sum of the fixed delay times in the data path. The data path is subdivided into n successive sections, each of which contains, at its input, a clock-controlled sampling element for accepting the data to be transmitted and has a propagation time that is considerably shorter than T.sub.min. The propagation time .tau..sub.n of the last section (Sn) is considerably greater than zero. The clock of the sampling elements is controlled using a version of the reference clock that has been delayed by T-.tau..sub.n.

Inventors: Kho; Rex (Holzkirchen, DE)

Assignee: Infineon Technologies AG

International Classification: G11C 7/00 (20060101); G11C 8/00 (20060101)

Expiration Date: 9/05/02018