Patent Number: 7,102,955

Title: Reduction of fusible links and associated circuitry on memory dies

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Inventors: Ayyapureddi; Sujeet V (Boise, ID), Seeram; Vasu (Colorado Springs, CO)

Assignee: Micron Technology, Inc.

International Classification: G11C 8/00 (20060101); G06F 11/00 (20060101); G06F 12/02 (20060101); G11C 17/18 (20060101); G11C 7/00 (20060101); G11C 7/10 (20060101)

Expiration Date: 9/05/02018