Patent Number: 7,103,038

Title: Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath

Abstract: A packet processing system converts a wide bus carrying P packets to a narrower bus that can carry only Q packets, where Q<P. The packet processing system includes a first data path, a queue, a shift register and a control unit. The first data path receives up to P packets during a first processing cycle. The queue stores the P packets in a queue. The control unit shifts a first quantity of data of the P packets into the shift register from the queue and selectively retrieves data from the shift register until a first packet of the plurality of packets is retrieved. The control unit then sends the first packet on a second data path during the first processing cycle.

Inventors: Gaudet; Brian (San Jose, CA)

Assignee: Juniper Networks, Inc.

International Classification: H04L 12/50 (20060101); G06F 3/05 (20060101); H04L 12/56 (20060101)

Expiration Date: 9/05/02018