Patent Number: 7,103,126

Title: Method and circuit for adjusting the timing of output data based on the current and future states of the output data

Abstract: A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Inventors: Joo; Yangsung (Boise, ID), Blodgett; Greg A. (Nampa, ID)

Assignee: Micron Technology, Inc.

International Classification: H04L 7/00 (20060101); H04L 7/02 (20060101)

Expiration Date: 9/05/02018