Patent Number: 7,103,128

Title: Data synchronization circuit and communication interface circuit

Abstract: There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

Inventors: Takeuchi; Katsuhiko (Kawasaki, JP), Sugahara; Hirohide (Kawasaki, JP), Utsunomiya; Shinichi (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: H04L 7/00 (20060101); H04L 25/00 (20060101); H04L 25/38 (20060101)

Expiration Date: 9/05/02018