Patent Number: 7,103,621

Title: Processor efficient transformation and lighting implementation for three dimensional graphics utilizing scaled conversion instructions

Abstract: Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.

Inventors: Rodriguez; Ricardo (Raleigh, NC), Jacobs; Marco (Einhoven, NL), Strube; David (Raleigh, NC)

Assignee: PTS Corporation

International Classification: G06F 7/00 (20060101); G06F 7/38 (20060101)

Expiration Date: 9/05/02018