Patent Number: 7,103,719

Title: System and method for managing a cache memory

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Inventors: Klein; Dean A. (Eagle, ID)

Assignee: Micron Technology, Inc.

International Classification: G06F 12/00 (20060101)

Expiration Date: 9/05/02018