Patent Number: 7,103,755

Title: Apparatus and method for realizing effective parallel execution of instructions in an information processor

Abstract: An apparatus for efficient parallel executing instruction avoiding the usage of cross bypasses, the apparatus including an instruction buffer for storing instructions, of decoders for decoding, in parallel, the instructions which simultaneously issue from the instruction buffer, executing units for executing the instructions decoded in the decoders, and an instruction-issuing controlling means for controlling the issuing of the instructions in such a way that, when the instructions are executed, one of the plural executing units executes instructions more frequently than the rest of the plural executing units. The apparatus is preferably incorporated in an information processor to superscalar or out-of-order instruction execution.

Inventors: Akiu; Susumu (Kawasaki, JP), Ukai; Masaki (Kawasaki, JP), Yoshida; Toshio (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G06F 9/30 (20060101); G06F 15/00 (20060101); G06F 9/40 (20060101)

Expiration Date: 9/05/02018