Patent Number: 7,103,861

Title: Test structure for automatic dynamic negative-bias temperature instability testing

Abstract: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUT's).

Inventors: Ang; Chew Hoe (Singapore, SG), Chen; Gang (Singapore, SG), Tan; Shyue Seng (Singapore, SG)

Assignee: Chartered Semiconductor Manufacturing Ltd.

International Classification: G06F 17/50 (20060101)

Expiration Date: 9/05/02018