Patent Number: 7,103,862

Title: Method to design and verify an integrated circuit device with multiple power domains

Abstract: A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.

Inventors: Sung; Nai-Yin (Hsin Chu, TW), Huang; Hsing-Chien (Hsin Chu, TW), Tsai; Jan-Hun (HsinChu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: G06F 17/50 (20060101)

Expiration Date: 9/05/02018