Patent Number: 7,103,869

Title: Method of verifying IC mask sets

Abstract: A method of fabricating an IC includes forming a test circuit in/on the wafer to electrically indicate that a correct mask set was used during a revision of the IC design during the manufacturing process. The readout of the circuit enables the manufacturer to immediately identify that an incorrect mask set was used, thereby preventing any improperly fabricated devices from being shipped to the customer. The test circuit may be located either in a primary device area or in the corridors between the devices (ICs). In either case, the test circuit includes a plurality of test devices, each test device corresponding to a version of the mask set in which at least one mast level modification has been made. In one embodiment the test devices are verification arrays, each array including a multiplicity of n electrical paths electrically connected in parallel with one another and extending across n of the N (n.ltoreq.N) structural levels of the wafer/IC (e.g., the poly, window and metal levels). Each of the paths includes n actuatable, series-connected elements corresponding to the masks used to form the n structural levels. After the modification of any one of the masks in a particular version of a mask set, selected elements are actuated in the array to indicate a correct mask version. If an incorrect mask set has been used, the test circuit provides one output signal, whereas if the correct mask set was used, the test circuit provides a different output signal. Also disclosed is a semiconductor wafer that includes such a test circuit either within a primary IC area or within a corridor between ICs.

Inventors: Genetti; Wayne Andrew (Sanatoga, PA), Sotak; David George (Allentown, PA)

Assignee: Agere Systems Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 9/05/02018