Patent Number: 7,132,317

Title: Method of manufacturing a semiconductor device that includes changing the internal stress of a conductive film

Abstract: There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress.

Inventors: Arao; Tatsuya (Atsugi, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

International Classification: H01L 21/00 (20060101)

Expiration Date: 2019-11-07 0:00:00