Patent Number: 7,132,318

Title: Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage

Abstract: Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

Inventors: Bonges, III; Henry A. (Milton, VT), Harmon; David L. (Essex Junction, VT), Hook; Terence B. (Jericho, VT), Lai; Wing L. (Williston, VT)

Assignee: International Business Machines Corporation

International Classification: H01L 21/00 (20060101); H01L 21/336 (20060101); H01L 21/8234 (20060101)

Expiration Date: 2019-11-07 0:00:00