Patent Number: 7,132,336

Title: Method and apparatus for forming a memory structure having an electron affinity region

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

Inventors: Aronowitz; Sheldon (San Jose, CA), Zubkov; Vladimir (Mountain View, CA), Sun; Grace S. (Mountain View, CA)

Assignee: LSI Logic Corporation

International Classification: H01L 21/336 (20060101)

Expiration Date: 2019-11-07 0:00:00