Patent Number: 7,132,686

Title: Semiconductor device and method of fabricating the same

Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

Inventors: Yamazaki; Shunpei (Tokyo, JP), Asami; Taketomi (Kanagawa, JP), Takayama; Toru (Kanagawa, JP), Kawasaki; Ritsuko (Kanagawa, JP), Adachi; Hiroki (Kanagawa, JP), Sakamoto; Naoya (Kanagawa, JP), Hayakawa; Masahiko (Kanagawa, JP), Shibata; Hiroshi (Kanagawa, JP), Arai; Yasuyuki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

International Classification: H01L 29/04 (20060101); H01L 31/036 (20060101); H01L 31/0376 (20060101); H01L 31/20 (20060101)

Expiration Date: 2019-11-07 0:00:00