Patent Number: 7,132,687

Title: Semiconductor device and method of manufacturing the same

Abstract: To improve the operation characteristic and reliability of a semiconductor device by optimizing the structure of bottom gate type or inverted stagger type TFTs arranged in circuits of the semiconductor device in accordance with the function of the respective circuits. At least LDD regions that overlap with a gate electrode are formed in an N channel type TFT of a driving circuit, and LDD regions that do not overlap with the gate electrode are formed in an N channel type TFT of a pixel matrix circuit. The concentration of the two kinds of LDD regions is differently set from each other, to thereby obtain the optimal circuit operation.

Inventors: Kawasaki; Ritsuko (Kanagawa, JP), Kitakado; Hidehito (Hyogo, JP), Kasahara; Kenji (Kanagawa, JP), Yamazaki; Shunpei (Tokyo, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

International Classification: H01L 29/04 (20060101)

Expiration Date: 2019-11-07 0:00:00