Patent Number: 7,132,704

Title: Transistor sidewall spacer stress modulation

Abstract: A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteristic is deposited over the gate electrode (116). The stress characteristics of at least a portion of the spacer film is then modulated (132, 192) and the spacer film (124) is etched to form sidewall spacers (160, 162) on the gate electrode sidewalls. The spacer film (124) is an LPCVD silicon nitride in one embodiment. Modulating (132) the spacer film (124) includes implanting Xenon or Germanium into the spacers (160) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant (132) may be performed selectively or non-selectively either before or after etching the spacer film (124).

Inventors: Grudowski; Paul A. (Austin, TX)

Assignee: Freescale Semiconductor, Inc.

International Classification: H01L 29/76 (20060101)

Expiration Date: 2019-11-07 0:00:00