Patent Number: 7,132,725

Title: Semiconductor device

Abstract: A p-channel MOSFET 1 has a buried layer 9 between a substrate 2 and an epitaxial layer 3. The impurity concentration of the buried layer 9 is higher than that of the epitaxial layer 3. As a result, if the p-channel MOSFET 3 and an n-channel MOSFET are fabricated in a single semiconductor substrate and when a voltage is applied between the source electrode 13 and the drain electrode 12, the impurity concentration of the epitaxial layer 3 apparently increases. Thus, the charge balance of the p-channel MOSFET 1 is not lost.

Inventors: Iwabuchi; Akio (Saitama, JP)

Assignee: Sanken Electric Co., Ltd.

International Classification: H01L 29/72 (20060101)

Expiration Date: 2019-11-07 0:00:00