Patent Number: 7,132,738

Title: Semiconductor device having multiple semiconductor chips stacked in layers and method for manufacturing the same, circuit substrate and electronic apparatus

Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.

Inventors: Tomimatsu; Hiroyuki (Sakata, JP)

Assignee: Seiko Epson Corporation

International Classification: H01L 23/02 (20060101)

Expiration Date: 2019-11-07 0:00:00