Patent Number: 7,132,848

Title: Power management circuit

Abstract: A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs, a first PMOS transistor and a second PMOS transistor. A first switch is coupled between a power voltage, the power control signal and the logic cell. A latch circuit coupled between the power voltage and the data signal outputs preserves the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.

Inventors: Lai; Fang-Shi (Chia Yi, TW)

Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.

International Classification: H03K 19/003 (20060101)

Expiration Date: 2019-11-07 0:00:00