Patent Number: 7,132,869

Title: Zero idle time Z-state circuit for phase-locked loops, delay-locked loops, and switching regulators

Abstract: The four types of the zero idle time Z-state circuits are presented with an improvement in productivity, cost, chip area, power consumption, and design time. The zero idle time Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding output of the sensing gate. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts in all three systems such as all kinds of phase-locked loops, delay-locked loops, and switching regulators. Thus, all the zero idle time Z-state circuits within all three systems make the initial condition close to the expected condition in order to enable these systems to come into lock or regulation quickly. Thus, all the zero idle time Z-state circuits utilizing less than twelve transistors presented achieve a fast lock-in time, a solution for harmonic locking problem, a minimization of start-up time, a initial reduction in power and time, a significant reduction in design simulation time, an improvement in productivity, and a higher performance.

Inventors: Park; Sangbeom (Tracy, CA)

Assignee: ANA Semiconductor

International Classification: H03K 3/02 (20060101)

Expiration Date: 2019-11-07 0:00:00