Patent Number: 7,133,819

Title: Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices

Abstract: Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.

Inventors: Hutton; Michael D. (Mountain View, CA)

Assignee: Altera Corporation

International Classification: G06F 17/50 (20060101); H03K 19/00 (20060101)

Expiration Date: 2019-11-07 0:00:00