Patent Number: 7,133,945

Title: Scalable I/O signaling topology using source-calibrated reference voltages

Abstract: An embodiment of the invention is a scalable I/O interface signaling technology for improved communication between semiconductor devices. In one embodiment, a system contains a first semiconductor device that includes a first characterization mechanism, a control logic coupled to the first characterization mechanism, a voltage generating mechanism coupled to the control logic and a transmit buffer. The control logic adjusts at least a first voltage generated by the voltage generating mechanism based on at least a value determined by the first characterization mechanism. The first voltage is coupled to the transmit buffer to define at least a transmit voltage signal level. In an alternate embodiment, the first voltage is coupled to a receive buffer in a second semiconductor device to define at least a receive voltage signal level.

Inventors: Lau; Benedict C. (San Jose, CA)

Assignee: Rambus Inc.

International Classification: G06F 13/00 (20060101); G11C 5/14 (20060101)

Expiration Date: 2019-11-07 0:00:00