Patent Number: 7,133,962

Title: Circulator chain memory command and address bus topology

Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.

Inventors: Leddige; Michael W. (Beaverton, OR), McCall; James A. (Beaverton, OR)

Assignee: Intel Corporation

International Classification: G06F 12/00 (20060101)

Expiration Date: 2019-11-07 0:00:00