Patent Number: 7,133,970

Title: Least mean square dynamic cache-locking

Abstract: A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.

Inventors: Vaidya; Priva N. (Shrewsbury, MA), Khan; Moinul H. (Austin, TX)

Assignee: Intel Corporation

International Classification: G06F 12/12 (20060101)

Expiration Date: 2019-11-07 0:00:00