Patent Number: 7,133,981

Title: Prioritized bus request scheduling mechanism for processing devices

Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.

Inventors: Hill; David L (Cornellus, OR), Bachand; Derek T. (Portland, OR)

Assignee: Intel Corporation

International Classification: G06F 13/00 (20060101)

Expiration Date: 2019-11-07 0:00:00