Patent Number: 7,133,996

Title: Memory device and internal control method therefor

Abstract: A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

Inventors: Ikeda; Shinichiro (Kasugai, JP), Kato; Yoshiharu (Kasugai, JP)

Assignee: Fujitsu Limited

International Classification: G06F 12/06 (20060101)

Expiration Date: 2019-11-07 0:00:00