Patent Number: 7,134,047

Title: Firmwave mechanism for correcting soft errors

Abstract: A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.

Inventors: Quach; Nhon (San Jose, CA)

Assignee: Intel Corporation

International Classification: G06F 11/00 (20060101); G06F 15/00 (20060101)

Expiration Date: 2019-11-07 0:00:00