Patent Number: 7,134,100

Title: Method and apparatus for efficient register-transfer level (RTL) power estimation

Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Inventors: Ravi; Srivaths (Princeton, NJ), Raghunathan; Anand (Plainsboro, NJ), Chakradhar; Srimat T. (Princeton, NJ)

Assignee: NEC USA, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-11-07 0:00:00