Patent Number: 7,232,692

Title: Photo-imaged stress management layer for semiconductor devices

Abstract: A photo-imaged stress management layer for a semiconductor device is described. The stress management layer is located on an outer surface of a semiconductor device and may be patterned to address certain stress compensation requirements of the semiconductor device. The stress management layer may be manufactured onto the semiconductor device using a photolithographic procedure that allows both simple and complex patterns to be realized.

Inventors: Guenter; James (Garland, TX), Hawthorne; Robert (Garland, TX), Aizpuru; Jose (Murphy, TX)

Assignee: Finisar Corporation

International Classification: H01L 21/00 (20060101)

Expiration Date: 2019-06-19 0:00:00